In many applications, interface circuits are configured to communicate data between system components using a master-slave communication protocol. Read and write data transactions between the master and slave interfaces are controlled by the master interface. For ease of reference, the term data transactions may be used to refer to read and/or write data transactions. A data transaction is initiated by the master interface, in response to data and/or control signals from a first logic circuit of the system. The master interface provides a message to the slave interface using a master-slave communication protocol. The slave interface is responsible for providing the message to a second logic circuit and providing an appropriate response back to the master interface. The data transaction is completed when the response is provided from the slave interface to the master interface. If an appropriate response is not received by a master interface, the master interface may wait indefinitely for a response from the slave circuit.
In communication systems that use master-slave communication protocols, the master interface is generally unaware of the status of the slave interface. The status of the slave interface may include, for example, busy, available, power-down, reset, and/or malfunctioning. If the slave interface is in a non-responsive state, a response may not be sent to the master interface to complete the data transaction. A master interface generally has a set of limited resources to manage pending data transactions. A data transaction that is initiated but is unable to complete takes up a portion of the resources of the master interface. Eventually, deadlock may occur if sufficient resources are not available to initiate additional transactions. Deadlock may affect subsequent data transactions with other slave interfaces. For example, an unresponsive slave interface may cause deadlock and prevent the master interface from initiating data transactions with other slave interfaces.
Ideally, a master interface is designed to detect and remedy such deadlock situations. However this is not always the case. Moreover, for some master-slave communication protocols, such as the AMBA-AXI protocol, interface circuits are provided as black box circuit designs (e.g., cores) that cannot easily be modified by a designer to include such safeguard functionality. Furthermore, deadlock situations can make it difficult to debug circuit designs utilizing master-slave communication protocols. For example, a circuit design may include a number of slave interfaces, any of which could cause deadlock if it becomes unresponsive.